`timescale 1ns/1ps
module first_one_top;
    reg [15:0] in;
    wire [4:0]out;
    initial begin
        in = 16'h0001;
        # 1 in = 16'h0002;
        # 1 in = 16'h0004;
        # 1 in = 16'h0010;
        # 1 in = 16'h0020;
        # 1 in = 16'h0040;
        # 1 in = 16'h0080;
        # 1 in = 16'h0100;
        # 1 in = 16'h0200;
        # 1 in = 16'h0400;
        # 1 in = 16'h0800;
        # 1 in = 16'h1000;
        # 1 in = 16'h2000;
        # 1 in = 16'h4000;
        # 1 in = 16'h8000;
        # 1 in = 16'h0000;
        # 1 in = 16'h0421;
        # 1 in = 16'h1204;
        # 1 in = 16'ha240;
        # 2 $stop;
    end

    first_one fo(out,in);

endmodule

module first_one(out,in);
    input [15:0]in;
    output reg [4:0]out;
    always @(*)
        casex(in)
            16'b0000_0000_0000_0000:out = 5'h10;
            16'bxxxx_xxxx_xxXX_XXX1:out = 5'h00;
            16'bxxxx_xxxx_xxXX_XX10:out = 5'h01;
            16'bxxxx_xxxx_xxXX_X100:out = 5'h02;
            16'bxxxx_xxxx_xxXX_1000:out = 5'h03;
            16'bxxxx_xxxx_xxX1_0000:out = 5'h04;
            16'bxxxx_xxxx_xx10_0000:out = 5'h05;
            16'bxxxx_xxxx_x100_0000:out = 5'h06;
            16'bxxxx_xxxx_1000_0000:out = 5'h07;
            16'bxxxx_xxx1_0000_0000:out = 5'h08;
            16'bxxxx_xx10_0000_0000:out = 5'h09;
            16'bxxxx_x100_0000_0000:out = 5'h0a;
            16'bxxxx_1000_0000_0000:out = 5'h0b;
            16'bxxx1_0000_0000_0000:out = 5'h0c;
            16'bxx10_0000_0000_0000:out = 5'h0d;
            16'bx100_0000_0000_0000:out = 5'h0e;
            16'b1000_0000_0000_0000:out = 5'h0f;
        endcase
endmodule